A digital circuit design process involves design formulation and specification, register transfer level (RTL) coding, functional and timing verification and synthesis. The design specification among other things specifies the throughput, area and power requirements that the design is expected to meet. A description of a digital circuit, usually in very-high-speed integrated circuits (VHSIC) hardware description language (VHDL) or Verilog, undergoes synthesis using vendor specific synthesis tools. VHDL and Verilog are examples of hardware description languages used for programming a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). A common design synthesis tool flow involves a number of phases which vary depending on the toolchain vendor. For example, synthesis using the Xilinx® toolchain involves a number of steps including Synthesis, Translate, MAP, PAR, and Bitgen, ultimately producing a bitstream file to program the FPGA if the synthesis is successful. The synthesis toolchain also produces design statistics such as the area occupied by the design, the maximum clock frequency and the approximate power consumption.
As a part of the design specification, the designer either has a specific throughput requirement for the application or the designer may simply want to achieve the best possible throughput. The clock frequency at which a design operates at is usually directly proportional to throughput. When a design has throughput requirements, the design is subject to timing constraints during synthesis. The synthesis toolchain reports whether the timing constraints are satisfied—the design is said to have timing-closure. In case one or more timing constraints are not satisfied, the design undergoes manual iteration and resynthesis until all the constraints are met. This is time consuming and possibly intrusive because ultimately the actual description of the hardware at the source level must change.
When there are no specific throughput requirements (i.e., the best throughput is desired), the synthesis process is usually applied without any timing constraints, and the synthesis tool reports the operating frequency it achieved.
In either case described above, the existing methodology for synthesis and timing-closure either requires manual iteration and tuning of the design or absent a thorough iterative process, a design may not achieve the best possible clock frequency. Some of the challenges are attributed to the non-linear behavior of the synthesis tool. Non-linearity with respect to timing-closure means the synthesis tool may report failure at a clock frequency contrainted to 100 MHz but success at a clock frequency of 110 MHz. The non-linearity implies that one cannot stop exploring higher clock frequencies simply because a lower clock frequency fails in timing-closure.